1. Field of the Invention
The present invention relates to data communication and more particularly to acquisition of a clock signal associated with the data communication.
2. Description of the Related Art
Communication systems frequently transmit data in which the clock is embedded in the data stream rather than sent as a separate signal. When the data stream is received, a clock and data recovery circuit recovers the embedded clock and retimes the received data to the recovered clock. Traditionally, a phase-locked loop (PLL) has been used to perform the clock recovery operation. FIG. 1 shows a block diagram of a traditional PLL configured for a clock and data recovery application. The phase-locked loop 100 includes a phase detector 102, which receives the input data signal conveyed on node 104 and also receives the VCO output clock signal conveyed on node 106 from the voltage controlled oscillator (VCO) 108. The phase detector 102 generates an error signal 110, which is a function of the phase difference between the input data signal and the VCO output clock signal. The phase detector 102 may also include additional circuitry to generate the reconstructed data on output node 114.
In order to help the VCO acquire the frequency of the input data stream, it has been common to use a reference clock to center the VCO output frequency for a nominal output that approximates the frequency of the input data stream. In a typical application, the VCO will multiply the reference clock by a predetermined (or selectable factor), e.g., 16, to achieve the nominal VCO output. For example, if the multiplication factor is 16, for a 2.7 Gbps data rate, the reference clock is 168.75 MHz. The requirement for a reference clock (generally differential) adds both cost and design complexity to the system in which a clock and data recovery circuit resides. The clock has to be supplied by a relatively high cost crystal oscillator component and distributed to the clock and data recovery circuit using design practices appropriate for high speed clock signals.
In addition to using the reference clock to center the nominal output of the PLL, the reference clock is also used to determine whether lock has been achieved. Typical lock-detect circuitry compares the reference clock to a divided down version of the recovered clock, and if the difference between the two clocks is sufficiently high, the PLL is determined to be out-of-lock.
It would be desirable to be able to provide a communication system that can acquire a clock signal embedded in an input data stream without having to use a reference signal. That would both save pins on the clock and data recovery integrated circuit and release the system from the cost and design complexity of having to supply a reference clock.